1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits and, more particularly, to the formation of connections between contact areas thereon, such as contact studs or metal lines.
2. Description of the Prior Art
Integrated circuits are now well known and, in recent years have become increasingly complex and densely integrated. The electrical elements within the integrated circuits have also been constructed according to higher performance designs, usually involving an increased number of layers in the construction thereof. Even simple integrated circuits invariably require some electrical connections between individual elements, such as transistors, of which the integrated circuit is constituted.
As complexity, density and circuit element performance has increased, the difficulty of making connections has increased. The success of making such connections has been limited because of the inherent physical properties of the materials used while there have been substantial increases in the quality required in such connections. For instance, as chip size has increased connections of increased length have been required. As integration density has increased, the width of connections has decreased. Further, increased integration density often requires a connection to traverse severe topology, which can engender connection defects while ever greater defect free lengths of connection must be formed. Even if connections can be formed with acceptable manufacturing yields under such conditions, increased length and reduced width both contribute to increased resistance of the connection, particularly when the connections must be formed of semiconductor materials.
Specifically, highly conductive materials such as copper and tungsten cannot generally be used other than at the surface of the integrated circuit (e.g. over all active layers but beneath a final protective oxide layer) due to difficulty in dry etching and patterning of such materials. The formation of metal connections at lower levels is also made difficult since further processing at high temperatures causes silicidation of the metals which causes such connections to become discontinuous over severe topology. Therefore, at lower levels of the integrated circuit, metal silicide (e.g. polysilicon which has undergone silicidation) connections, such as TiSi.sub.2, have been typically used. However, this material is particularly susceptible of becoming discontinuous when deposited over severe topologies of complex, multi-layered integrated circuit structures and also limits conductivity to the 100-200 .mu.ohm-cm range.
Further, it is clear that all connections required in an integrated circuit cannot be made in the same layer because complex circuits will seldom be free of crossing conductors. The formation of insulators for such crossing conductors requires additional processing steps, increasing integrated circuit cost, and complicates the roughness of the topology over which such connections must be formed. As the number of layers of the integrated circuit is increased, the roughness of the topology of the integrated circuit simultaneously increases the defect-free length of conductor which is required and increases the likelihood of a defect occurring within any given length of conductor.
Additionally, both conductors and insulators must be formed at each level, substantially increasing the number of processing steps for each additional layer of connections which is required in the device. The number of processing steps is also increased in the present technology by the additional steps required to form studs for interconnecting different connection layers.
Further, voltage drops within an integrated circuit can pose limitations on design both from the standpoint of heat dissipation and operating voltage margins. No method has heretofore existed to allow connections to be made with low resistance metals at lower layers within the integrated circuit device.